Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system

In order to investigate the performance potential of three-dimensional integrated circuits (3-D IC's) for high performance computer systems a comparative study of the interconnect structure of a RISC processor/cache system is presented. The wiring structure, wiring dimensions and line drivers a...

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Bibliographic Details
Published in:IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging packaging, and manufacturing technology. Part B, Advanced packaging, 1996-11, Vol.19 (4), p.719-727
Main Authors: Kuhn, S.A., Kleiner, M.B., Ramm, P., Weber, W.
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Driver circuits
Electronics
Exact sciences and technology
High performance computing
Integrated circuit interconnections
Integrated circuits
Multichip modules
Power dissipation
Power system interconnection
Printed circuits
Reduced instruction set computing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Three-dimensional integrated circuits
Wiring
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Summary:In order to investigate the performance potential of three-dimensional integrated circuits (3-D IC's) for high performance computer systems a comparative study of the interconnect structure of a RISC processor/cache system is presented. The wiring structure, wiring dimensions and line drivers are optimized for 3-D system alternatives. The realizations are compared to a conventional printed circuit board (PCB) and a typical multichip module (MCM) implementation of the system with respect to cache access time and power dissipation. The impact of electrical parameters of interconnection lines as well as associated package parasitics on second level cache read access is investigated. Case studies show reductions of effective switching capacitances of more than an order of magnitude and reductions of second level cache access time of over 30% for optimized 3-D systems compared to conventional PCB realizations.
ISSN:1070-9894
1558-3686
DOI:10.1109/96.544362