A 100 W 5.1-Channel Digital Class-D Audio Amplifier With Single-Chip Design

A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2012-06, Vol.47 (6), p.1344-1354
Main Authors: LIU, Jia-Ming, CHIEN, Shih-Hsiung, KUO, Tai-Haur
Format: Article
Language:English
Subjects:
5.1-channel
Amplifiers
Applied sciences
audio amplifier
Audio equipment
Circuit properties
class-D amplifier
delta-sigma modulator
Design. Technologies. Operation analysis. Testing
Digital circuits
DSM
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Integrated circuits
Logic gates
Periodic structures
power stage
Pulse width modulation
pulse-width modulation (PWM)
SDM
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal to noise ratio
Switches
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Description
Summary:A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm 2 .
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2012.2188465