Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications

This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are in...

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Bibliographic Details
Published in:IEEE electron device letters 2012-09, Vol.33 (9), p.1234-1236
Main Authors: Chang-Woo Sohn, Chang Yong Kang, Rock-Hyun Baek, Do-Young Choi, Hyun Chul Sagong, Eui-Young Jeong, Chang-Ki Baek, Jeong-Soo Lee, Lee, J. C., Yoon-Ha Jeong
Format: Article
Language:English
Subjects:
Analytic model
Applied sciences
Capacitance
Cutoff frequency
Electronics
Exact sciences and technology
fin height
fin spacing
fin-based multigate field-effect transistors (FETs) (FinFETs)
FinFETs
Logic gates
Nanoscale devices
parasitic capacitance
Radio frequency
radio frequency (RF)
Resistance
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
series resistance
Transistors
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Summary:This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are included in a small-signal circuit. It is found that reducing the fin-spacing-to-fin-height ratio of FinFETs, as long as it is compatible with the process integration, is desirable for improving RF performance. This is because the current-gain cutoff frequency and the maximum oscillation frequency are affected by decreasing parasitic capacitance more than by increasing series resistance.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2012.2204853