New Insight Into PBTI Evaluation Method for nMOSFETs With Stacked High- k/IL Gate Dielectric

In this letter, a strategy to minimize the error in lifetime projections using a positive bias temperature instability (PBTI) test has been proposed. Two distinctly different projection slopes were observed in a plot of time to failure versus oxide electric field. A small slope in the high-field reg...

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Bibliographic Details
Published in:IEEE electron device letters 2012-11, Vol.33 (11), p.1517-1519
Main Authors: Sang Kyung Lee, Minseok Jo, Chang-Woo Sohn, Chang Yong Kang, Lee, J. C., Yoon-Ha Jeong, Byoung Hun Lee
Format: Article
Language:English
Subjects:
Applied sciences
Electron traps
Electronics
Exact sciences and technology
Hafnium compounds
hbox{HfO}_{2}
High K dielectric materials
lifetime
Logic gates
MOSFETs
nMOSFET
positive bias temperature instability (PBTI)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Stress
Transistors
trap cluster
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Summary:In this letter, a strategy to minimize the error in lifetime projections using a positive bias temperature instability (PBTI) test has been proposed. Two distinctly different projection slopes were observed in a plot of time to failure versus oxide electric field. A small slope in the high-field region, which means weaker electric field dependence, led to an underestimation of lifetime. This result was attributed to a filled trap cluster at a specific trap energy level, locally reducing the oxide electric field. Thus, different lifetimes can be projected depending on stress bias. Maintaining a PBTI stress bias range below this trap energy level is recommended for accurate projections.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2012.2211072