A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS

• Published in: IEEE journal of solid-state circuits 2013-01, Vol.48 (1), p.118-127
• Main Authors: Hsu, S. K., Agarwal, A., Anders, M. A., Mathew, S. K., Kaul, H., Sheikh, F., Krishnamurthy, R. K.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; crossbar; Design. Technologies. Operation analysis. Testing; Digital circuits; Direct power generation; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy efficiency; Energy measurement; Engines; Exact sciences and technology; flip-flop; Integrated circuits; Integrated optics. Optical fibers and wave guides; level shifter; Logic gates; Mathematical analysis; Multiplexing; near-threshold voltage (NTV); Optical and optoelectronic circuits; permutation; Permutations; register file; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Single instruction multiple data (SIMD); Switching, multiplexing, switched capacity circuits; ultra-low voltage; vector processing; Vectors; Vectors (mathematics); Voltage; Voltage measurement; {\rm V}_{\rm MIN}
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2012.2222811

An ultra-low voltage reconfigurable 4-way to 32-way SIMD vector permutation engine is fabricated in 22 nm tri-gate bulk CMOS, consisting of a 32-entry × 256b 3-read/1-write ported register file with a 256b byte-wise any-to-any permute crossbar for 2-dimensional shuffle. The register file integrates a vertical shuffle across multiple entries into read/write operations, and includes clock-less static reads with shared P/N dual-ended transmission gate (DETG) writes, improving register file V MIN by 250 mV across PVT variations with a wide dynamic operating range of 280 mV-1.1 V. The permute crossbar implements an interleaved folded byte-wise multiplexer layout forming an any-to-any fully connected tree to perform a horizontal shuffle with permute accumulate circuits, and includes vector flip-flops, stacked min-delay buffers, shared gates, and ultra-low voltage split-output (ULVS) level shifters improving logic V MIN by 150 mV, while enabling peak energy efficiency of 585 GOPS/W measured at 260 mV, 50 °C. The permutation engine achieves: (i) nominal register file performance of 1.8 GHz, 106 mW measured at 0.9 V, 50 °C, (ii) robust register file functionality measured down to 280 mV with peak energy efficiency of 154 GOPS/W, (iii) scalable permute crossbar performance of 2.9 GHz, 69 mW measured at 1.1 V, 50 °C with sub-threshold operation at 240 mV, 10 MHz consuming 19 μW, and (iv) a 64b 4 × 4 matrix transpose algorithm and AoS to SoA conversion with 40%-53% energy savings and 25%-42% improved peak throughput measured at 1.8 GHz, 0.9 V.