A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier

• Published in: IEEE journal of solid-state circuits 2013-04, Vol.48 (4), p.1009-1017
• Main Authors: KIM, Kwangseok, KIM, Young-Hwa, YU, Wonsik, CHO, Seonghwan
• Format: Article
• Language: English
• Subjects: Accuracy; Amplifiers; Applied sciences; Calibration; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); CMOS integrated circuits; CMOS process; Delay; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Logic gates; PLL and all-digital PLL (ADPLL); Quantization; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; time amplifier; time- domain ADC; Time-to-digital converter (TDC); two-step architecture
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2237996

In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate, and programmable gain for a wide input range. Using the proposed pulse-train time amplifier, a 7-bit two-step TDC is implemented. The proposed TDC employs repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. The prototype chip fabricated in 65 nm CMOS process achieves 3.75 ps of time resolution at 200 MS/s while consuming 3.6 mW and occupying 0.02 mm 2 area. Compared to previously reported TDCs, the proposed TDC achieves the fastest conversion rate and the best FoM without any calibration.