High-Speed Hybrid Superconductor-to-Semiconductor Interface Circuit With Ultra-Low Power Consumption

Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybr...

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Bibliographic Details
Published in:IEEE transactions on applied superconductivity 2013-06, Vol.23 (3), p.1400104-1400104
Main Authors: Ortlepp, T., Whiteley, S. R., Lizhen Zheng, Xiaofan Meng, Van Duzer, T.
Format: Article
Language:English
Subjects:
Applied sciences
Bit error rate
Circuit properties
Clocks
CMOS integrated circuits
Delay
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Interface
Josephson junction
Power demand
RSFQ
Semiconductor device measurement
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Superconducting devices
superconductor electronics
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Summary:Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10 -12 . We will discuss the trade-off among circuit robustness, speed, and power consumption.
ISSN:1051-8223
1558-2515
DOI:10.1109/TASC.2012.2227918