A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver

• Published in: IEEE journal of solid-state circuits 2013-07, Vol.48 (7), p.1669-1679
• Main Authors: Carballido, J., Hermosillo, J., Veloz, A., Arditti, D., Del Rio, A., Borrayo, E., Guzman, M. E., Lakdawala, H., Verhelst, M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Built-in self-test; Calibration; Design. Technologies. Operation analysis. Testing; Electronics; Engines; Exact sciences and technology; Integrated circuits; IQ imbalance; manufacturing; PAPD; radio; Radio frequency; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SoC; System-on-chip; testing; Testing, measurement, noise and reliability; transceiver; Transceivers
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2253401

This paper presents a flexible and portable digital framework for Built-in Self-Test (BIST) and calibration of RF/analog circuitry. Novel to the proposed testing framework, is a reusable, flexible, drop-in IP core, composed of a centralized custom processing engine with data path, memory architecture and instruction set optimized for efficient execution of compute intensive test and calibration algorithms. The innovative BIST engine is complemented with a calibration and test sequencing methodology exploiting the embedded test hardware, to dynamically correct for transceiver imbalances and non-idealities, as well as to estimate performance parameters such as Error Vector Magnitude (EVM). The engine has been integrated with a WiFi transceiver in a 32 nm SoC test chip to demonstrate the functionality of this framework. This implementation covers an area of 0.63 mm 2 and provides similar performance (e.g., improvements up to 10 dB in EVM for Rx IQ imbalance compensation) to off-chip testing without relying on expensive equipment.