A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radios. The TDC consumes 3 mW from a 1...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2013-07, Vol.48 (7), p.1721-1729
Main Authors: Hyung Seok Kim, Ornelas, C., Chandrashekar, K., Shi, D., Pin-en Su, Madoglio, Paolo, Li, William Y., Ravi, Ashoke
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Clocks
Computer architecture
Delays
Design. Technologies. Operation analysis. Testing
Digital circuits
DPLL
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
fractional-n
Integrated circuits
mismatch insensitive TDC
Phase locked loops
Phase noise
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Shift registers
Signal convertors
WiFi
WiMax
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Summary:A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radios. The TDC consumes 3 mW from a 1.05-V supply and occupies an area of 0.004 mm 2 . A digital frequency-locked loop is used to track and correct for PVT variations in the TDC and no additional linearization or mismatch calibrations are required. The DPLL uses a 20-bit high dynamic range DAC to drive a VCO in order to effectively realize a DCO with 100-Hz frequency resolution. The 2.5-GHz WiFi band LO output is generated from a 40-MHz reference with an integrated phase noise of - 35 dBc (10 kHz to 10 MHz) while consuming 21 mW . The worst case spur in the LO output is below - 50 dBc without requiring TDC mismatch and linearity calibration.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2013.2253407