Unified Endurance Degradation Model of Floating Gate NAND Flash Memory

Endurance degradation model applicable to the broad node range of floating-gate NAND flash memory is proposed for the first time. The model is based on generation of the trapped charge, which follows nonuniform spatial distribution of the erase tunneling current. A special Topology Computer-Aided De...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electron devices 2013-06, Vol.60 (6), p.2031-2037
Main Authors: Fayrushin, A., Chang-Hyun Lee, Youngwoo Park, Jeong-Hyuk Choi, Chilhee Chung
Format: Article
Language:English
Subjects:
Applied sciences
Ash
Calibration
Circuit properties
Computational modeling
Degradation
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electron traps
Electronic circuits
Electronics
Endurance
Exact sciences and technology
flash memories
Integrated circuits
Integrated circuits by function (including memories and processors)
modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Tunneling
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Endurance degradation model applicable to the broad node range of floating-gate NAND flash memory is proposed for the first time. The model is based on generation of the trapped charge, which follows nonuniform spatial distribution of the erase tunneling current. A special Topology Computer-Aided Design (TCAD) simulation technique to simulate program/erase cycling is described in detail. Simulation parameters, determining change of midgap voltage (vertical centroid position and maximum value of the trapped charge) are extracted from the reference device with known endurance curve, and these are applied to the target cell. The endurance characteristics predicted by the model are verified to reproduce measured endurance curves for design rules of 27, 42, and 90 nm. Several factors affect midgap voltage change-area occupied by trapped charge; vertical position of charge centroid; separation of trapped charge distribution and tunnel current. A 3-D TCAD simulation allows accurate consideration of the given factors, resulting in good match between measured and simulated endurance curves.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2013.2256789