700 V ultra-low on-resistance DB-nLDMOS with optimised thermal budget and neck region

An ultra-low Ron,sp 700 V DB-nLDMOS (dual P-buried-layer nLDMOS) which uses 0.35 μm technology and full ion implantation technology is proposed. Experimental results show that with 800 V BVds, Ron,sp is only 10.7 Ω · mm2 which is the lowest value of triple RESURF (REduce SURface Field) LDMOS reporte...

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Bibliographic Details
Published in:Electronics letters 2014-01, Vol.50 (3), p.209-211
Main Authors: Mao, Kun, Qiao, Ming, Li, Zhaoji, Zhang, Bo
Format: Article
Language:English
Subjects:
Applied sciences
Budgeting
dual P‐buried‐layer nLDMO
Electronics
Exact sciences and technology
full ion implantation technology
Implantation
Ion implantation
JFET
JFET effect
junction gate field effect transistors
MOS integrated circuits
MOSFET
neck region
Necks
reduce surface field
RESURF
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductor technology
size 0.35 mum
Technology utilization
thermal budget optimisation
Transistors
ultra‐ow on‐resistance DB‐nLDMOS
voltage 700 V
voltage 800 V
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Summary:An ultra-low Ron,sp 700 V DB-nLDMOS (dual P-buried-layer nLDMOS) which uses 0.35 μm technology and full ion implantation technology is proposed. Experimental results show that with 800 V BVds, Ron,sp is only 10.7 Ω · mm2 which is the lowest value of triple RESURF (REduce SURface Field) LDMOS reported before. This mainly benefits from two aspects. First, thermal budgets of the process are strictly limited after implantation of the Pbury layer. Secondly, device sizes of the neck region are optimised to reduce Ron,sp which also suppress the JFET effect of the triple RESURF LDMOS.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2013.2287