Reduction of Positive-Bias-Stress Effects in Bulk-Accumulation Amorphous-InGaZnO TFTs

We report an abnormal negative threshold-voltage shift (ΔVTH) in bulk-accumulation (dual-gate driven) amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs) after application of positive-bias-stress (PBS). In devices annealed at 250°C for 2 h in vacuum, the negative ΔVTH is accompanied with subthre...

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Bibliographic Details
Published in:IEEE electron device letters 2014-05, Vol.35 (5), p.560-562
Main Authors: Seonghyun Jin, Tae-Woong Kim, Young-Gug Seol, Mativenga, Mallory, Jin Jang
Format: Article
Language:English
Subjects:
a-IGZO
Annealing
Applied sciences
Charge carrier processes
dual gate
Electronics
Exact sciences and technology
Iron
Logic gates
PBS
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
TFT
Thermal stability
Thin film transistors
Transistors
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Summary:We report an abnormal negative threshold-voltage shift (ΔVTH) in bulk-accumulation (dual-gate driven) amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs) after application of positive-bias-stress (PBS). In devices annealed at 250°C for 2 h in vacuum, the negative ΔVTH is accompanied with subthreshold swing degradation, consistent with PBS-induced defect creation. Negative-bias-stress induces negligible ΔVTH, ruling out ion migration in the gate-insulator. By varying the top-gate length, it is found that the negligible ΔVTH is a function of bulk-accumulation. However, after vacuum annealing at 250°C for 100 h, PBS induces negligible ΔVTH, verifying that the negative ΔVTH in short-time annealed devices is related to defects in the bulk a-IGZO. Therefore, good PBS stability can be achieved in bulk-accumulation dual-gate a-IGZO TFTs by long-time vacuum anneal.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2014.2311172