Loading…
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-netwo...
Saved in:
Published in: | Chronic diseases and translational medicine 2014-05, Vol.8 (3), p.148-162 |
---|---|
Main Authors: | , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites |
Online Access: | Request full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | cdi_FETCH-LOGICAL-c3515-c4168309d1664a8fb3dda7fc8dd2a1c5c16e554f66768d0290f9abf25dcdb5c83 |
container_end_page | 162 |
container_issue | 3 |
container_start_page | 148 |
container_title | Chronic diseases and translational medicine |
container_volume | 8 |
creator | Beldachi, Arash Farhadi Hollis, Simon Nunez-Yanez, Jose L |
description | This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free. |
doi_str_mv | 10.1049/iet-cdt.2013.0087 |
format | article |
fullrecord | <record><control><sourceid>proquest_24P</sourceid><recordid>TN_cdi_pascalfrancis_primary_28507045</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>3092306804</sourcerecordid><originalsourceid>FETCH-LOGICAL-c3515-c4168309d1664a8fb3dda7fc8dd2a1c5c16e554f66768d0290f9abf25dcdb5c83</originalsourceid><addsrcrecordid>eNqFkE1LxDAURYso-PkD3BXEhYuOL22Tpu50nFFhwM0I7kKajzHaacakRcZfb0qHQVBxlbc45768G0WnCEYI8vLSqDYRsh2lgLIRAC12ogNUYJRQgp53tzOg_ejQ-1cATDDQg-hTPbeqkUrGc-s6HzvbtaZZxLxeWGfal2WsrYsb1X5Y9-YT2yTixayuYv4HKdcNXxrB63odOyVso82ic7yq1Y-Q42hP89qrk817FD1NJ_PxfTJ7vHsYX88SkWGEE5EjQjMoJSIk51RXmZS80IJKmXIksEBEYZxrQgpCJaQl6JJXOsVSyAoLmh1FZ0Puytn3TvmWvdrONWElC7FpBoRCHig0UMJZ753SbOXMkrs1Q8D6ilmomIWKWV8x6ysOzvkmmftwsna8EcZvxZRiKCDHgbsauA9Tq_X_wWx8O09vpgCDfDHIPbb9-cNk3lPfnJXUgU1-Yf8-4Aso4a68</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>3092306804</pqid></control><display><type>article</type><title>eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip</title><source>Wiley Open Access</source><creator>Beldachi, Arash Farhadi ; Hollis, Simon ; Nunez-Yanez, Jose L</creator><creatorcontrib>Beldachi, Arash Farhadi ; Hollis, Simon ; Nunez-Yanez, Jose L</creatorcontrib><description>This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.</description><identifier>ISSN: 1751-8601</identifier><identifier>ISSN: 1751-861X</identifier><identifier>ISSN: 2095-882X</identifier><identifier>EISSN: 1751-861X</identifier><identifier>EISSN: 2589-0514</identifier><identifier>DOI: 10.1049/iet-cdt.2013.0087</identifier><language>eng</language><publisher>Stevenage: The Institution of Engineering and Technology</publisher><subject>Algorithms ; application behaviour ; Applied sciences ; Circuit properties ; Communication ; Design ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Error correction & detection ; Exact sciences and technology ; eXtended Torus routing algorithm for networks‐on‐chip ; Field programmable gate arrays ; FPGA ; Hierarchies ; inner‐torus building blocks ; Integrated circuits ; mesh generation ; mesh topology ; network‐on‐chip ; nonregular global topologies ; Performance evaluation ; resource availability ; Routers ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; topology ; XTRANC algorithm</subject><ispartof>Chronic diseases and translational medicine, 2014-05, Vol.8 (3), p.148-162</ispartof><rights>The Institution of Engineering and Technology</rights><rights>2014 The Institution of Engineering and Technology</rights><rights>2015 INIST-CNRS</rights><rights>Copyright John Wiley & Sons, Inc. 2014</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c3515-c4168309d1664a8fb3dda7fc8dd2a1c5c16e554f66768d0290f9abf25dcdb5c83</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1049%2Fiet-cdt.2013.0087$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://www.proquest.com/docview/3092306804?pq-origsite=primo$$EHTML$$P50$$Gproquest$$Hfree_for_read</linktohtml><link.rule.ids>314,780,784,9755,11562,25753,27924,27925,37012,44590,46052,46476</link.rule.ids><linktorsrc>$$Uhttps://onlinelibrary.wiley.com/doi/abs/10.1049%2Fiet-cdt.2013.0087$$EView_record_in_Wiley-Blackwell$$FView_record_in_$$GWiley-Blackwell</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=28507045$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Beldachi, Arash Farhadi</creatorcontrib><creatorcontrib>Hollis, Simon</creatorcontrib><creatorcontrib>Nunez-Yanez, Jose L</creatorcontrib><title>eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip</title><title>Chronic diseases and translational medicine</title><description>This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.</description><subject>Algorithms</subject><subject>application behaviour</subject><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Communication</subject><subject>Design</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Error correction & detection</subject><subject>Exact sciences and technology</subject><subject>eXtended Torus routing algorithm for networks‐on‐chip</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>Hierarchies</subject><subject>inner‐torus building blocks</subject><subject>Integrated circuits</subject><subject>mesh generation</subject><subject>mesh topology</subject><subject>network‐on‐chip</subject><subject>nonregular global topologies</subject><subject>Performance evaluation</subject><subject>resource availability</subject><subject>Routers</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>topology</subject><subject>XTRANC algorithm</subject><issn>1751-8601</issn><issn>1751-861X</issn><issn>2095-882X</issn><issn>1751-861X</issn><issn>2589-0514</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>PIMPY</sourceid><recordid>eNqFkE1LxDAURYso-PkD3BXEhYuOL22Tpu50nFFhwM0I7kKajzHaacakRcZfb0qHQVBxlbc45768G0WnCEYI8vLSqDYRsh2lgLIRAC12ogNUYJRQgp53tzOg_ejQ-1cATDDQg-hTPbeqkUrGc-s6HzvbtaZZxLxeWGfal2WsrYsb1X5Y9-YT2yTixayuYv4HKdcNXxrB63odOyVso82ic7yq1Y-Q42hP89qrk817FD1NJ_PxfTJ7vHsYX88SkWGEE5EjQjMoJSIk51RXmZS80IJKmXIksEBEYZxrQgpCJaQl6JJXOsVSyAoLmh1FZ0Puytn3TvmWvdrONWElC7FpBoRCHig0UMJZ753SbOXMkrs1Q8D6ilmomIWKWV8x6ysOzvkmmftwsna8EcZvxZRiKCDHgbsauA9Tq_X_wWx8O09vpgCDfDHIPbb9-cNk3lPfnJXUgU1-Yf8-4Aso4a68</recordid><startdate>201405</startdate><enddate>201405</enddate><creator>Beldachi, Arash Farhadi</creator><creator>Hollis, Simon</creator><creator>Nunez-Yanez, Jose L</creator><general>The Institution of Engineering and Technology</general><general>Institution of Engineering and Technology</general><general>John Wiley & Sons, Inc</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>3V.</scope><scope>7X7</scope><scope>7XB</scope><scope>8FI</scope><scope>8FJ</scope><scope>8FK</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>FYUFA</scope><scope>GHDGH</scope><scope>K9.</scope><scope>M0S</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope></search><sort><creationdate>201405</creationdate><title>eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip</title><author>Beldachi, Arash Farhadi ; Hollis, Simon ; Nunez-Yanez, Jose L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3515-c4168309d1664a8fb3dda7fc8dd2a1c5c16e554f66768d0290f9abf25dcdb5c83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Algorithms</topic><topic>application behaviour</topic><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Communication</topic><topic>Design</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Error correction & detection</topic><topic>Exact sciences and technology</topic><topic>eXtended Torus routing algorithm for networks‐on‐chip</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>Hierarchies</topic><topic>inner‐torus building blocks</topic><topic>Integrated circuits</topic><topic>mesh generation</topic><topic>mesh topology</topic><topic>network‐on‐chip</topic><topic>nonregular global topologies</topic><topic>Performance evaluation</topic><topic>resource availability</topic><topic>Routers</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>topology</topic><topic>XTRANC algorithm</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Beldachi, Arash Farhadi</creatorcontrib><creatorcontrib>Hollis, Simon</creatorcontrib><creatorcontrib>Nunez-Yanez, Jose L</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>ProQuest Central (Corporate)</collection><collection>Health & Medical Collection</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>Hospital Premium Collection</collection><collection>Hospital Premium Collection (Alumni Edition)</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>ProQuest Central (Alumni)</collection><collection>ProQuest Central</collection><collection>ProQuest Central Essentials</collection><collection>AUTh Library subscriptions: ProQuest Central</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central</collection><collection>Health Research Premium Collection</collection><collection>Health Research Premium Collection (Alumni)</collection><collection>ProQuest Health & Medical Complete (Alumni)</collection><collection>Health & Medical Collection (Alumni Edition)</collection><collection>Publicly Available Content Database (Proquest) (PQ_SDU_P3)</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><jtitle>Chronic diseases and translational medicine</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Beldachi, Arash Farhadi</au><au>Hollis, Simon</au><au>Nunez-Yanez, Jose L</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip</atitle><jtitle>Chronic diseases and translational medicine</jtitle><date>2014-05</date><risdate>2014</risdate><volume>8</volume><issue>3</issue><spage>148</spage><epage>162</epage><pages>148-162</pages><issn>1751-8601</issn><issn>1751-861X</issn><issn>2095-882X</issn><eissn>1751-861X</eissn><eissn>2589-0514</eissn><abstract>This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.</abstract><cop>Stevenage</cop><pub>The Institution of Engineering and Technology</pub><doi>10.1049/iet-cdt.2013.0087</doi><tpages>15</tpages><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1751-8601 |
ispartof | Chronic diseases and translational medicine, 2014-05, Vol.8 (3), p.148-162 |
issn | 1751-8601 1751-861X 2095-882X 1751-861X 2589-0514 |
language | eng |
recordid | cdi_pascalfrancis_primary_28507045 |
source | Wiley Open Access |
subjects | Algorithms application behaviour Applied sciences Circuit properties Communication Design Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Error correction & detection Exact sciences and technology eXtended Torus routing algorithm for networks‐on‐chip Field programmable gate arrays FPGA Hierarchies inner‐torus building blocks Integrated circuits mesh generation mesh topology network‐on‐chip nonregular global topologies Performance evaluation resource availability Routers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices topology XTRANC algorithm |
title | eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T13%3A14%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_24P&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=eXtended%20Torus%20routing%20algorithm%20for%20networks-on-chip:%20a%20routing%20algorithm%20for%20dynamically%20reconfigurable%20networks-on-chip&rft.jtitle=Chronic%20diseases%20and%20translational%20medicine&rft.au=Beldachi,%20Arash%20Farhadi&rft.date=2014-05&rft.volume=8&rft.issue=3&rft.spage=148&rft.epage=162&rft.pages=148-162&rft.issn=1751-8601&rft.eissn=1751-861X&rft_id=info:doi/10.1049/iet-cdt.2013.0087&rft_dat=%3Cproquest_24P%3E3092306804%3C/proquest_24P%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c3515-c4168309d1664a8fb3dda7fc8dd2a1c5c16e554f66768d0290f9abf25dcdb5c83%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=3092306804&rft_id=info:pmid/&rfr_iscdi=true |