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eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip

This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-netwo...

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Published in:Chronic diseases and translational medicine 2014-05, Vol.8 (3), p.148-162
Main Authors: Beldachi, Arash Farhadi, Hollis, Simon, Nunez-Yanez, Jose L
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Hollis, Simon
Nunez-Yanez, Jose L
description This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.
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identifier ISSN: 1751-8601
ispartof Chronic diseases and translational medicine, 2014-05, Vol.8 (3), p.148-162
issn 1751-8601
1751-861X
2095-882X
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2589-0514
language eng
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source Wiley Open Access
subjects Algorithms
application behaviour
Applied sciences
Circuit properties
Communication
Design
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Error correction & detection
Exact sciences and technology
eXtended Torus routing algorithm for networks‐on‐chip
Field programmable gate arrays
FPGA
Hierarchies
inner‐torus building blocks
Integrated circuits
mesh generation
mesh topology
network‐on‐chip
nonregular global topologies
Performance evaluation
resource availability
Routers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
topology
XTRANC algorithm
title eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
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