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Design and optimization of impurity- and electrostatically-doped superlattice FETs to meet all the ITRS power targets at VDD = 0.4 V

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Bibliographic Details
Main Authors: MAIORANO, P, GNANI, E, GNUDI, A, REGGIANI, S, BACCARANI, G
Format: Conference Proceeding
Language:English
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ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2014.06.020