Delay-fault testability preservation of the concurrent decomposition and factorization transformations

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 1995-05, Vol.14 (5), p.582-590
• Main Authors: El-Maleh, A.H., Rajski, J.
• Format: Article
• Language: English
• Subjects: Applied sciences; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuit manufacture; Integrated circuit synthesis; Integrated circuits; Logic testing; Propagation delay; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sufficient conditions
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.384420

In this paper, we study the testability preservation of the concurrent decomposition and factorization transformations under several delay-fault testing constraints. We show that all transformations, except dual extraction of multiplexor structures, preserve testability with respect to a general Robust Path-Delay-Fault (RPDF) test set, Validatable Nonrobust (VNR) delay-fault test set, and Delay Verification (DV) test set. In addition, we provide new, sufficient conditions for the algebraic resubstitution with complement transformation to preserve RPDF, VNR, and DV testability, that cover a larger class of complementary expressions than was known previously. Experimental results on a set of Berkeley PLA's and MCNC benchmark circuits show that dual extraction of multiplexor structures is utilized in only 2 out of 50 benchmark circuits. We demonstrate that while disabling this transformation has negligible effect on area, it results in an efficient test-set preserving multilevel logic synthesis algorithm, that preserves testability with respect to RPDF, VNR, and DV test sets.< >