A wafer level testability approach based on an improved scan insertion technique

Testing strategies for complex WSI systems are one of the elements that may prevent the full exploitation of novel technologies, such as multichip modules (MCM's), because of the limited reliability (and quality) of the final product. The application of an efficient test strategy to the circuit...

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Bibliographic Details
Published in:IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging packaging, and manufacturing technology. Part B, Advanced packaging, 1995-08, Vol.18 (3), p.438-447
Main Authors: Bolchini, C., Buonanno, G., Ferrandi, F., Sciuto, D., Bombana, M., Cavalloro, P.
Format: Article
Language:English
Subjects:
Aging
Applied sciences
Circuit testing
Costs
Design for testability
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Multichip modules
Performance analysis
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
System testing
Test equipment
Time to market
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Summary:Testing strategies for complex WSI systems are one of the elements that may prevent the full exploitation of novel technologies, such as multichip modules (MCM's), because of the limited reliability (and quality) of the final product. The application of an efficient test strategy to the circuits of the module is necessary to achieve high-quality, cost-effective devices. The aim of this paper is to introduce a structured approach to the design of testable wafer scale devices. Bare die testability is guaranteed through the application mainly of the partial scan methodology, to provide the most convenient solution in terms of overhead and performance, while module testability is achieved through the application of the boundary scan technique.< >
ISSN:1070-9894
1558-3686
DOI:10.1109/96.404100