A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1993-11, Vol.28 (11), p.1092-1098
Main Authors: Sugibayashi, T., Takeshima, T., Naritake, I., Matano, T., Takada, H., Aimoto, Y., Furuta, K., Fujita, M., Saeki, T., Sugawara, H., Murotani, T., Kasai, N., Shibahara, K., Nakajima, K., Hada, H., Hamada, T., Aizaki, N., Kunio, T., Kakehashi, E., Masumori, K., Tanigawa, T.
Format: Article
Language:English
Subjects:
Application software
Applied sciences
Capacitors
Circuits
CMOS technology
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Portable computers
Power dissipation
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Time sharing computer systems
Voltage
Wiring
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Summary:A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.245587