GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8/spl times/2(MUX)/2/spl times/8(DEMUX) data conversion processes,...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1994-07, Vol.29 (7), p.808-814
Main Authors: Higashisaka, N., Shimada, M., Ohta, A., Hosogi, K., Tobita, Y., Mitsui, Y.
Format: Article
Language:English
Subjects:
Applied sciences
Clocks
Data conversion
Degradation
Electronics
Exact sciences and technology
Gallium arsenide
Integrated circuits
Integrated circuits by function (including memories and processors)
MESFETs
Multiplexing
Optical fiber communication
Power dissipation
Power supplies
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Shift registers
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Summary:GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8/spl times/2(MUX)/2/spl times/8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-/spl mu/m BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.303718