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Cascade of ultrafast soliton-dragging and trapping logic gates
As part of the header decoding circuit for a 100-Gb/s ring local area network, a soliton-dragging NOR gate followed by a soliton-trapping AND gate that can operate up to bit rates of 0.2 THz was demonstrated. The soliton-dragging NOR gate has a time-shift-keyed output, while the soliton-trapping AND...
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Published in: | IEEE photonics technology letters 1992-09, Vol.4 (9), p.1043-1046 |
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container_end_page | 1046 |
container_issue | 9 |
container_start_page | 1043 |
container_title | IEEE photonics technology letters |
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creator | Soccolich, C.E. Chbat, M.W. Islam, M.N. Prucnal, P.R. |
description | As part of the header decoding circuit for a 100-Gb/s ring local area network, a soliton-dragging NOR gate followed by a soliton-trapping AND gate that can operate up to bit rates of 0.2 THz was demonstrated. The soliton-dragging NOR gate has a time-shift-keyed output, while the soliton-trapping AND gate converts the time shifts to an energy contrast. Even with timing jitter and coupling losses, the measured output energy contrast is approximately 12:1. The experimental results are in good agreement with numerical simulations of the nonlinear Schrodinger equation.< > |
doi_str_mv | 10.1109/68.157143 |
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The experimental results are in good agreement with numerical simulations of the nonlinear Schrodinger equation.< ></description><subject>Bit rate</subject><subject>Circuits</subject><subject>Decoding</subject><subject>Energy measurement</subject><subject>Exact sciences and technology</subject><subject>Fundamental areas of phenomenology (including applications)</subject><subject>Local area networks</subject><subject>Logic gates</subject><subject>Loss measurement</subject><subject>Numerical simulation</subject><subject>Optics</subject><subject>Physics</subject><subject>Quantum optics</subject><subject>Schrodinger equation</subject><subject>Timing jitter</subject><issn>1041-1135</issn><issn>1941-0174</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1992</creationdate><recordtype>article</recordtype><recordid>eNpFkM1LxDAQxYMouK4evHrqQQQPXWeaNG0ugix-wYIXPYfZNCmRbluT7sH_3iwVfZd5w_zmHR5jlwgrRFB3sl5hWaHgR2yBSmAOWInj5CF5RF6esrMYPwFQlFws2P2aoqHGZoPL9t0UyFGcsjh0fhr6vAnUtr5vM-qbLB3H8bB0Q-tN1tJk4zk7cdRFe_E7l-zj6fF9_ZJv3p5f1w-b3HCQUy6UICvctrRolOQFKHDQmC00TiYVKKmgpMqKGkA4V4MjJ_jWiQIVAV-ymzl3DMPX3sZJ73w0tuuot8M-6qIuSikUT-DtDJowxBis02PwOwrfGkEfGtKy1nNDib3-DT100LlAvfHx70HwSiLHhF3NmLfW_sfNGT_KpmzO</recordid><startdate>19920901</startdate><enddate>19920901</enddate><creator>Soccolich, C.E.</creator><creator>Chbat, M.W.</creator><creator>Islam, M.N.</creator><creator>Prucnal, P.R.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19920901</creationdate><title>Cascade of ultrafast soliton-dragging and trapping logic gates</title><author>Soccolich, C.E. ; Chbat, M.W. ; Islam, M.N. ; Prucnal, P.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c306t-494ae4fb5e1c9632090f0dcb0df6666216a2aaaa7e48004ff80faf43bf4219a03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1992</creationdate><topic>Bit rate</topic><topic>Circuits</topic><topic>Decoding</topic><topic>Energy measurement</topic><topic>Exact sciences and technology</topic><topic>Fundamental areas of phenomenology (including applications)</topic><topic>Local area networks</topic><topic>Logic gates</topic><topic>Loss measurement</topic><topic>Numerical simulation</topic><topic>Optics</topic><topic>Physics</topic><topic>Quantum optics</topic><topic>Schrodinger equation</topic><topic>Timing jitter</topic><toplevel>online_resources</toplevel><creatorcontrib>Soccolich, C.E.</creatorcontrib><creatorcontrib>Chbat, M.W.</creatorcontrib><creatorcontrib>Islam, M.N.</creatorcontrib><creatorcontrib>Prucnal, P.R.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE photonics technology letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Soccolich, C.E.</au><au>Chbat, M.W.</au><au>Islam, M.N.</au><au>Prucnal, P.R.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Cascade of ultrafast soliton-dragging and trapping logic gates</atitle><jtitle>IEEE photonics technology letters</jtitle><stitle>LPT</stitle><date>1992-09-01</date><risdate>1992</risdate><volume>4</volume><issue>9</issue><spage>1043</spage><epage>1046</epage><pages>1043-1046</pages><issn>1041-1135</issn><eissn>1941-0174</eissn><coden>IPTLEL</coden><abstract>As part of the header decoding circuit for a 100-Gb/s ring local area network, a soliton-dragging NOR gate followed by a soliton-trapping AND gate that can operate up to bit rates of 0.2 THz was demonstrated. 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issn | 1041-1135 1941-0174 |
language | eng |
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source | IEEE Xplore (Online service) |
subjects | Bit rate Circuits Decoding Energy measurement Exact sciences and technology Fundamental areas of phenomenology (including applications) Local area networks Logic gates Loss measurement Numerical simulation Optics Physics Quantum optics Schrodinger equation Timing jitter |
title | Cascade of ultrafast soliton-dragging and trapping logic gates |
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