An NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall MOS transistor (NBiBMOS transistor)

• Published in: IEEE electron device letters 1992-11, Vol.13 (11), p.563-565
• Main Authors: O, K.K., Lutsky, J.J., Reif, R.L., Lee, H.-S.
• Format: Article
• Language: English
• Subjects: Applied sciences; BiCMOS integrated circuits; Bipolar transistor circuits; Bipolar transistors; Electronics; Exact sciences and technology; Fabrication; Logic circuits; Logic gates; Merging; MOS devices; MOSFETs; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Voltage
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/55.192840

The concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (V/sub CE/ or V/sub DE/) is less than the turn-on voltage of the n-p-n bipolar transistor (V/sub BE/= approximately 0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy approximately 1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased.< >