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A new structure for CMOS realization of MVL functions

A new structure is proposed for the realization of multiple-valued logic (MVL) functions. Multiple-valued logic levels are represented in terms of current values, which represent the inputs and the outputs of the MVL circuits. Binary voltage signals are generated inside the structure by using a circ...

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Bibliographic Details
Published in:International journal of electronics 1993-02, Vol.74 (2), p.251-263
Main Authors: JAIN, A. K., ABD-EL-BARR, M. H., BOLTON, R. J.
Format: Article
Language:English
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Summary:A new structure is proposed for the realization of multiple-valued logic (MVL) functions. Multiple-valued logic levels are represented in terms of current values, which represent the inputs and the outputs of the MVL circuits. Binary voltage signals are generated inside the structure by using a circuit element called threshold. Using these voltage signals and binary operators, such as AND, OR, XOR and inverter, binary voltage signals are obtained and used as control signals for generating the output current levels for the desired MVL function. The realizations of some example MVL circuits using the proposed structure are included along with HSPICE transient analysis simulation results to verify the functionality of the designed circuits.
ISSN:0020-7217
1362-3060
DOI:10.1080/00207219308925832