Design aspects of MOS-controlled thyristor elements: technology, simulation, and experimental results

• Published in: IEEE transactions on electron devices 1991-07, Vol.38 (7), p.1605-1611
• Main Authors: Bauer, F., Halder, E., Hofmann, K., Haddon, H., Roggwiller, P., Stockmeier, T., Burgler, J., Fichtner, W., Muller, S., Westermann, M., Moret, J.-M., Vuilleumier, R.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuits; Current density; Electronics; Exact sciences and technology; Insulated gate bipolar transistors; Insulation; MOS devices; Other multijunction devices. Power transistors. Thyristors; Power electronics; Power semiconductor devices; Power semiconductor switches; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Thyristors; Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.85156

2.5-kV thyristor devices have been fabricated with integrated MOS controlled n/sup +/-emitter shorts and a bipolar turn-on gate using a p-channel DMOS technology. Square-cell geometries with pitch variations ranging from 15 to 30 mu m were implemented in one- and two-dimensional arrays with up to 20000 units. The impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures. By realizing MOS components with submicrometer channel lengths, scaled single cells are shown to turn off with current densities of several kiloamperes per square centimeter at a gate bias of 5 V. In the case of multi-cell ensembles, turn-off performance is limited due to inhomogeneous current distribution. Critical process parameters as well as the device behavior were optimized through multidimensional numerical simulation.< >