Design for testability techniques for CMOS combinational gates

• Published in: IEEE transactions on instrumentation and measurement 1991-08, Vol.40 (4), p.703-708
• Main Authors: Buonanno, G., Lombardi, F., Sciuto, D., Shen, Y.-N.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit faults; Circuit properties; Circuit testing; CMOS technology; Combinational circuits; Design for testability; Digital circuits; Electric, optical and optoelectronic circuits; Electrical fault detection; Electronic circuits; Electronics; Exact sciences and technology; Fault detection; Impedance; Integrated circuit modeling; Semiconductor device modeling
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/19.85338

The design of easily testable CMOS combinational circuits is discussed. Two CMOS structured design techniques are presented. The novelty of this approach is the complete fault detection of single- and multiple-line stuck-at, transistor stuck-open, and stuck-on faults for combinational circuits. The test algorithm requires only minimal modifications to detect a large number of bridging faults. These techniques are both based on the addition of two transistors, a P-FET and an N-FET, which are placed in series between the P and N sections. In the first case (dynamic fully CMOS, DFCMOS), the transistors are controlled by a single input; in the other case (testable fully CMOS, TFCMOS), there is one input for each additional transistor. The test procedure is presented, and it is shown that multiple fault detection can be easily achieved.< >