N-channel depletion-mode InP FET with enhanced barrier height gates

The fabrication of an n-channel depletion-mode InP field-effect transistor (FET) with enhanced barrier height gates, using a surface passivation technique that substantially increases the barrier height ( Phi /sub b/=0.83 eV) of InP, is reported. The transistors demonstrate characteristics with exce...

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Bibliographic Details
Published in:IEEE electron device letters 1989-08, Vol.10 (8), p.370-372
Main Authors: Iliadis, A.A., Lee, W., Aina, O.A.
Format: Article
Language:English
Subjects:
Applied sciences
Chemical technology
Electronics
Exact sciences and technology
Fabrication
FETs
Indium phosphide
Insulation
Leakage current
Metallization
Oxidation
Passivation
Schottky barriers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
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Summary:The fabrication of an n-channel depletion-mode InP field-effect transistor (FET) with enhanced barrier height gates, using a surface passivation technique that substantially increases the barrier height ( Phi /sub b/=0.83 eV) of InP, is reported. The transistors demonstrate characteristics with excellent pinch-off, flat saturation, transconductance in the range of 60-68 mS/mm, and no indication of the onset of breakdown for drain-source biases in excess of 35 V. They are shown to be highly stable, with no observable drain current drift over a period of more than 24 h of testing under DC bias. The high stability and performance of these devices demonstrate the potential for the gate metallization of InP.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.31760