Failure in CMOS circuits induced by hot carriers in multi-gate transistors

The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is analyzed. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection f...

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Bibliographic Details
Published in:IEEE electron device letters 1988-11, Vol.9 (11), p.564-566
Main Authors: Chatterjee, A., Aur, S.-W., Niuya, T., Yang, P., Seitchik, J.A.
Format: Article
Language:English
Subjects:
Applied sciences
Charge carrier processes
Circuit testing
CMOS technology
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hot carriers
Impact ionization
Integrated circuits
Isolation technology
Life estimation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Substrate hot electron injection
Temperature sensors
Voltage
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Summary:The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is analyzed. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection from multi-gate p-channel transistors with interdigitated source and drain. The electron current generated from impact ionization near the drain forward biases the source junctions, causing hole injection to the substrate. The current is sensitive to the supply voltage and temperature. Consequently, unanticipated failures may occur at the high voltages and temperatures encountered during burn-in. Design and process solutions are discussed.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.9277