MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache

MIPS-X is a 32-b RISC microprocessor implemented in a conservative 2-/spl mu/m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includ...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 1987-10, Vol.22 (5), p.790-799
Main Authors: Horowitz, M., Chow, P., Stark, D., Simoni, R.T., Salz, A., Przybylski, S., Hennessy, J., Gulak, G., Agarwal, A., Acken, J.M.
Format: Article
Language:English
Subjects:
Applied sciences
Bandwidth
Clocks
CMOS technology
Electronics
Engines
Exact sciences and technology
Integrated circuits
Microprocessors
Pipeline processing
Process design
Reduced instruction set computing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
Throughput
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Summary:MIPS-X is a 32-b RISC microprocessor implemented in a conservative 2-/spl mu/m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includes a 2-kbyte on-chip instruction cache. The authors provide an overview of MIPS-X, focusing on the techniques used to reduce the complexity of the processor and implement the on-chip instruction cache.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1987.1052815