Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage ¿V for a given current. An empirical equation describing ¿V in te...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2010-05, Vol.57 (5), p.1003-1008
Main Authors: Ryu, Kevin Kyungbum, Nausieda, Ivan, He, David Da, Akinwande, Akintunde Ibitayo, Bulovic, Vladimir, Sodini, Charles G
Format: Article
Language:English
Subjects:
Applied sciences
Bias
Devices
Electronics
Exact sciences and technology
Field-effect transistor (FETs)
Gates
Logic gates
Mathematical model
Mathematical models
organic compounds
Pentacene
reliability
Saturation
Semiconductor device measurement
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
stability
Stress
Stresses
Thin film transistors
Thin films
thin-film transistors (TFTs)
Transistors
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Summary:The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage ¿V for a given current. An empirical equation describing ¿V in terms of different gate and drain bias stress measurements and stress times is presented and verified. In the measured devices, ¿ V saturates at 14 V, independent of the gate bias-stress condition. A model based on carrier trapping rate equation that accounts for this ¿V saturation is developed. The model suggests that the ¿V saturation is due to the small density of traps compared to the channel carrier density.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2010.2044282