A Space Vector Switching Strategy for Three-Level Five-Phase Inverter Drives

A novel space vector modulation (SVM) technique for a three-level five-phase inverter is described based on an optimized five vectors concept. The concept utilizes a novel vector minimization technique that reduces the number of vectors in the d 1 - q 1 vector space by identifying candidate vectors...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on industrial electronics (1982) 2010-07, Vol.57 (7), p.2332-2343
Main Authors: Liliang Gao, Fletcher, John E
Format: Article
Language:English
Subjects:
Capacitors
Computational modeling
d_{1}{-}q_{1} vector space
d_{3}{-}q_{3} vector space
Electric potential
Fault tolerance
Induction machines
Inverters
Mathematical analysis
Medium voltage
optimized five vectors (OFV)
Power system harmonics
region
Space vector pulse width modulation
Support vector machines
Switching
three level five phase
Torque control
Vector space
Vector spaces
Vectors (mathematics)
Voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A novel space vector modulation (SVM) technique for a three-level five-phase inverter is described based on an optimized five vectors concept. The concept utilizes a novel vector minimization technique that reduces the number of vectors in the d 1 - q 1 vector space by identifying candidate vectors in each of the ten sectors that comprise the decagon vector space. The candidate vectors are selected based on the inequality relationship between the five-phase voltages during each switching cycle. Using this technique, the original 243 inverter states are reduced to 113 candidate vectors, and from the remaining states ten possible switching sequences in each sector are utilized to develop the desired voltage reference in the d 1 - q 1 vector space while forcing a null vector in the d 3 - q 3 vector space. A novel region determination technique is also introduced to identify the subregion that the d 1 - q 1 voltage vector occupies. This technique significantly reduces the computational overhead required when implementing SVM techniques with multilevel and multiphase inverters. The space vector technique can utilize redundant vectors to assist in balancing subcycle variation of the dc-link capacitor voltage under unbalanced load conditions. Experiments validate simulation results where the low-order voltage harmonics show that the d 3 - q 3 voltage vector is null.
ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2009.2033087