Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon-Germanium Source/Drain

• Published in: IEEE electron device letters 2010-10, Vol.31 (10), p.1074-1076
• Main Authors: Baudot, S, Andrieu, F, Weber, O, Perreau, P, Damlencourt, J, Barnola, S, Salvetat, T, Tosti, L, Brevard, L, Lafond, D, Eymery, J, Faynot, O
• Format: Article
• Language: English
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Logic gates; MOSFET circuits; MOSFETs; Performance evaluation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Silicon germanium; silicon-germanium (SiGe); silicon-on-insulator (SOI) technology; Strain; Substrates; Transistors
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2010.2057500

Strained p-MOSFETs with recessed and embedded silicon-germanium (eSiGe) source/drain (S/D) are fabricated on either silicon-on-insulator (SOI) or strained SOI (sSOI) substrates of 15-nm body thickness. For a gate voltage overdrive of -1 V and a gate length L of 60 nm, p-MOSFETs on SOI (sSOI) with eSiGe exhibit a 37% (18%) saturation drive current enhancement compared to standard sSOI structures with Si S/D. The low field mobility and series resistance are extracted in order to understand the performance boost induced by the eSiGe process. The significant I_ON improvement of SOI pMOS with eSiGe S/D compared to sSOI pMOS with Si S/D is attributed to a 65% mobility enhancement and to a 30% series-resistance reduction with respect to sSOI pMOS with Si S/D at L = 60 nm.