Total Performance of 32-nm-Node Ultralow-[Formula Omitted]/Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica [Formula Omitted]

The total performance of low-[Formula Omitted]/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO, [Formula Omitted]) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by a...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2010-11, Vol.57 (11), p.2821
Main Authors: Oda, Noriaki, Chikaki, Shinichi, Kubota, Takeo, Nakao, Shinichi, Tomioka, Kazuhiro, Soda, Eiichi, Nakamura, Naofumi, Gawase, Akifumi, Nogawa, Jun, Kawashima, Yoshitsugu, Hayashi, Ryo, Suzuki, Tatsu, Saito, Shuichi
Format: Article
Language:English
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Summary:The total performance of low-[Formula Omitted]/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO, [Formula Omitted]) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is successfully achieved. The wiring capacitance showed 10% reduction, compared to the conventional porous SiOC (ULK, [Formula Omitted]). Sufficient interconnect reliability and packaging characteristics for the circuit-under-pad structure are also obtained. The predicted circuit performance was 8% higher than ULK in the 32-nm node.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2010.2066568