A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS

• Published in: IEEE journal of solid-state circuits 2010-11, Vol.45 (11), p.2312-2320
• Main Authors: Onouchi, M, Kanno, Y, Saen, M, Komatsu, S, Yasu, Y, Ishibashi, K
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clock synchronizer; Clocks; Delay; Design. Technologies. Operation analysis. Testing; dynamic voltage-and-frequency scaling (DVFS) control; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; low power; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Shift registers; Synchronization; System-on-a-chip; Voltage control
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2065610

Abstract-A wide-range voltage-and-frequency clock synchronizer (WRCS) for maintaining synchronization during dynamic voltage-and-frequency scaling was developed. The key feature of the WRCS is short-range skew measurement based on a predictive-delay-adjustment (PDA) scheme. The short-range skew measurement results in reduction of the area of the WRCS by 77%, that is, the area of the fabricated WRCS in a 40-nm CMOS process is only 5.65 × 10 -3 mm 2 . In the case of large voltage variation (0.8-1.55 V) and wide frequency range (100 MHz-1 GHz), measured skew is suppressed to the lowest percentage yet reported, namely, less than 6.8% of clock period. Moreover, current consumption of the WRCS is only 0.48 mA under 1.1-V 100-MHz operation.