Analysis of Common-Mode Noise for Weakly Coupled Differential Serpentine Delay Microstrip Line in High-Speed Digital Circuits

• Published in: IEEE transactions on electromagnetic compatibility 2012-06, Vol.54 (3), p.655-666
• Main Authors: SHIUE, Guang-Hwa, SHIU, Jia-Hung, TSAI, Yi-Chin, HSU, Che-Ming
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Common-mode noise; Crosstalk; crosstalk noise; Delay; Delay lines; differential serpentine delay line; differential-to-common mode conversion; Electric noise; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Integrated circuit modeling; length mismatch; Microstrip; mixed S-parameter; Noise; Systems, networks and services of telecommunications; Telecommunications; Telecommunications and information theory; Transient analysis; Transmission and modulation (techniques and equipments)
• ISSN: 0018-9375; 1558-187X
• DOI: 10.1109/TEMC.2011.2173765

This study investigates the mechanisms of generation of the transient transmission common-mode noise in a differential serpentine delay line under weak coupling condition. The generation mechanism and the frequency of common-mode noise are investigated with reference to the time-domain transmission waveform and the differential-to-common mode conversion mixed-mode S-parameters using the circuit solver HSPICE and 3-D full-wave simulator HFSS, respectively. The generation mechanisms of common-mode noise include length mismatch between vertical-turn-coupled traces, the length effect of parallel-coupled traces, and the crosstalk noise effect. Moreover, a graphical method based on wave tracing is presented to illustrate the cancellation mechanism of near-end common-mode noise for the symmetrical differential serpentine delay line. Some practical, commonly used layout routings of the differential serpentine delay line are investigated. Some important design guidelines are provided to help design differential serpentine delay line with low common-mode noise. A comparison between simulated and measured results validates the equivalent circuit model and analytical approach.