A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

• Published in: IEEE journal of solid-state circuits 2013-01, Vol.48 (1), p.150-158
• Main Authors: Karl, E., Yih Wang, Yong-Gee Ng, Zheng Guo, Hamzaoglu, F., Meterelliyoz, M., Keane, J., Bhattacharya, U., Zhang, K., Mistry, K., Bohr, M.
• Format: Article
• Language: English
• Subjects: Applied sciences; Arrays; Circuit properties; Circuits; CMOS; CMOS integrated circuits; Cobalt; Density; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Low voltage; Performance evaluation; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; semiconductor memory; Silicon; SRAM; Static random access memory; Transistors; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2012.2213513

A 162 Mb voltage-scalable SRAM array design in 22 nm CMOS tri-gate logic technology is presented. The designs of a 0.092 μm 2 bitcell for high density applications and a 0.108 μm 2 bitcell for improved performance at low supply voltage are introduced. Transient voltage collapse and wordline under-drive peripheral assist circuits improve low-voltage operating margins and address fin quantization. Co-optimization of tri-gate transistors and circuits allow up to 70% improvement in frequency at low voltages and 85% improvement in density from a scaled 32 nm design. The low-voltage array design demonstrates 4.6 GHz operation at 1.0 V and 3.4 GHz operation at 0.8 V while achieving array densities up to 6.7 Mb/mm 2 .