Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 ° C to -40 ° C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2012-12, Vol.59 (12), p.918-921
Main Authors: Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.
Format: Article
Language:English
Subjects:
Chips
Circuits
CMOS
Delay
Delay variations
Delays
device matrix array (DMA)
Gates
Integrated circuit modeling
Logic circuits
Logic gates
Low voltage
Semiconductor device measurement
sub-threshold
Temperature
Temperature dependence
Temperature measurement
Voltage measurement
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Summary:Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 ° C to -40 ° C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σ/μ of the gate delay is proportional to 1/ T for the first time, where T is the absolute temperature.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2012.2231038