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Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature
Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 ° C to -40 ° C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows...
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| Published in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2012-12, Vol.59 (12), p.918-921 |
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| Main Authors: | , , , , , , , |
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| cited_by | cdi_FETCH-LOGICAL-c394t-d71fa998923065d41664d1115606f97f327a21cafd9f146014d250a951ffd1143 |
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| cites | cdi_FETCH-LOGICAL-c394t-d71fa998923065d41664d1115606f97f327a21cafd9f146014d250a951ffd1143 |
| container_end_page | 921 |
| container_issue | 12 |
| container_start_page | 918 |
| container_title | IEEE transactions on circuits and systems. II, Express briefs |
| container_volume | 59 |
| creator | Takahashi, R. Takata, H. Yasufuku, T. Fuketa, H. Takamiya, M. Nomura, M. Shinohara, H. Sakurai, T. |
| description | Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 ° C to -40 ° C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σ/μ of the gate delay is proportional to 1/ T for the first time, where T is the absolute temperature. |
| doi_str_mv | 10.1109/TCSII.2012.2231038 |
| format | article |
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| identifier | ISSN: 1549-7747 |
| ispartof | IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.918-921 |
| issn | 1549-7747 1558-3791 |
| language | eng |
| recordid | cdi_proquest_journals_1283982793 |
| source | IEEE Xplore (Online service) |
| subjects | Chips Circuits CMOS Delay Delay variations Delays device matrix array (DMA) Gates Integrated circuit modeling Logic circuits Logic gates Low voltage Semiconductor device measurement sub-threshold Temperature Temperature dependence Temperature measurement Voltage measurement |
| title | Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature |
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