A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

• Published in: IEEE journal of solid-state circuits 2014-04, Vol.49 (4), p.812-826
• Main Authors: Jacquet, David, Hasbani, Frederic, Flatresse, Philippe, Wilson, Robin, Arnaud, Franck, Cesana, Giorgio, Di Gilio, Thierry, Lecocq, Christophe, Roy, Tanmoy, Chhabra, Amit, Grover, Chiranjeev, Minez, Olivier, Uginet, Jacky, Durieu, Guy, Adobati, Cyril, Casalotto, Davide, Nyer, Frederic, Menut, Patrick, Cathelin, Andreia, Vongsavady, Indavong, Magarshack, Philippe
• Format: Article
• Language: English
• Subjects: ARM Cortex A9; CMOS integrated circuits; CMOS technology; dual core processor; dynamic voltage and frequency scaling; Electrostatics; energy efficiency optimization; forward body bias; Logic gates; Silicon; Threshold voltage; Transistors; UTBB FD-SOI
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2295977

This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.