PADI, an Ultrafast Preamplifier - Discriminator ASIC for Time-of-Flight Measurements

The design of a general-purpose PreAmplifier-DIscriminator ASIC chip, PADI, is presented in this article. PADI is intended to be used as Front-End-Electronics (FEE) for reading out the timing Resistive-Plate Chambers (RPCs) in the time-of-flight (ToF) wall of the CBM detector for the future FAIR fac...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2014-04, Vol.61 (2), p.1015-1023
Main Authors: Ciobanu, M., Herrmann, N., Hildenbrand, K. D., Kis, M., Schuttauf, A., Flemming, H., Deppe, H., Lochner, S., Fruhauf, J., Deppner, I., Loizeau, P. A., Trager, M.
Format: Article
Language:English
Subjects:
Analog-digital integrated circuit
Application specific integrated circuits
ASIC
CMOS
Detectors
Impedance
Mirrors
Resistors
Semiconductor device measurement
Signal resolution
timing circuits
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Summary:The design of a general-purpose PreAmplifier-DIscriminator ASIC chip, PADI, is presented in this article. PADI is intended to be used as Front-End-Electronics (FEE) for reading out the timing Resistive-Plate Chambers (RPCs) in the time-of-flight (ToF) wall of the CBM detector for the future FAIR facility in Darmstadt-Germany, which will comprise about 100,000 channels in a 150 m 2 area. The evolution of this 0.18 μm CMOS technology design will be presented, from the first prototype PADI-1 to the last one, PADI-8, as well as its features and test results.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2014.2305999