Loading…

Fast Polar Decoders: Algorithm and Implementation

Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an orde...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE journal on selected areas in communications 2014-05, Vol.32 (5), p.946-957
Main Authors:	Sarkis, Gabi, Giard, Pascal, Vardy, Alexander, Thibeault, Claude, Gross, Warren J.
Format:	Article
Language:	English
Subjects:	Algorithms Architecture Channels Complexity theory Construction Decoders Decoding Field programmable gate arrays Hardware Maximum likelihood decoding Parity check codes polar codes Reliability storage systems successive-cancellation decoding Systematics Throughput
Citations:	Items that this one cites Items that cite this one
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

cited_by	cdi_FETCH-LOGICAL-c390t-69fb17fa41b1d71e45aaa58f32ef6d019ed3d77c76226ac8002a4c1c263fb6723
cites	cdi_FETCH-LOGICAL-c390t-69fb17fa41b1d71e45aaa58f32ef6d019ed3d77c76226ac8002a4c1c263fb6723
container_end_page	957
container_issue	5
container_start_page	946
container_title	IEEE journal on selected areas in communications
container_volume	32
creator	Sarkis, Gabi Giard, Pascal Vardy, Alexander Thibeault, Claude Gross, Warren J.
description	Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.
doi_str_mv	10.1109/JSAC.2014.140514
format	article
fullrecord	<record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_journals_1545894537</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6804939</ieee_id><sourcerecordid>1620106861</sourcerecordid><originalsourceid>FETCH-LOGICAL-c390t-69fb17fa41b1d71e45aaa58f32ef6d019ed3d77c76226ac8002a4c1c263fb6723</originalsourceid><addsrcrecordid>eNpdkD1PwzAURS0EEqWwI7FEYmFJec_fYasKhaJKIAGz5ToOBCVxsdOBf0-qIAamu5z79O4h5BxhhgjF9ePLfDGjgHyGHATyAzJBIXQOAPqQTEAxlmuF8picpPQJA8g1nRBc2tRnz6GxMbv1LpQ-ppts3ryHWPcfbWa7Mlu128a3vuttX4fulBxVtkn-7Den5G1597p4yNdP96vFfJ07VkCfy6LaoKosxw2WCj0X1lqhK0Z9JUvAwpesVMopSam0TgNQyx06Klm1kYqyKbka725j-Nr51Ju2Ts43je182CWDclgLUksc0Mt_6GfYxW74zqDgQhdcMDVQMFIuhpSir8w21q2N3wbB7B2avUOzd2hGh0PlYqzU3vs_XGrgBSvYD-mfat0</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1545894537</pqid></control><display><type>article</type><title>Fast Polar Decoders: Algorithm and Implementation</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Sarkis, Gabi ; Giard, Pascal ; Vardy, Alexander ; Thibeault, Claude ; Gross, Warren J.</creator><creatorcontrib>Sarkis, Gabi ; Giard, Pascal ; Vardy, Alexander ; Thibeault, Claude ; Gross, Warren J.</creatorcontrib><description>Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.</description><identifier>ISSN: 0733-8716</identifier><identifier>EISSN: 1558-0008</identifier><identifier>DOI: 10.1109/JSAC.2014.140514</identifier><identifier>CODEN: ISACEM</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Architecture ; Channels ; Complexity theory ; Construction ; Decoders ; Decoding ; Field programmable gate arrays ; Hardware ; Maximum likelihood decoding ; Parity check codes ; polar codes ; Reliability ; storage systems ; successive-cancellation decoding ; Systematics ; Throughput</subject><ispartof>IEEE journal on selected areas in communications, 2014-05, Vol.32 (5), p.946-957</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) May 2014</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c390t-69fb17fa41b1d71e45aaa58f32ef6d019ed3d77c76226ac8002a4c1c263fb6723</citedby><cites>FETCH-LOGICAL-c390t-69fb17fa41b1d71e45aaa58f32ef6d019ed3d77c76226ac8002a4c1c263fb6723</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6804939$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27922,27923,54794</link.rule.ids></links><search><creatorcontrib>Sarkis, Gabi</creatorcontrib><creatorcontrib>Giard, Pascal</creatorcontrib><creatorcontrib>Vardy, Alexander</creatorcontrib><creatorcontrib>Thibeault, Claude</creatorcontrib><creatorcontrib>Gross, Warren J.</creatorcontrib><title>Fast Polar Decoders: Algorithm and Implementation</title><title>IEEE journal on selected areas in communications</title><addtitle>J-SAC</addtitle><description>Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.</description><subject>Algorithms</subject><subject>Architecture</subject><subject>Channels</subject><subject>Complexity theory</subject><subject>Construction</subject><subject>Decoders</subject><subject>Decoding</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Maximum likelihood decoding</subject><subject>Parity check codes</subject><subject>polar codes</subject><subject>Reliability</subject><subject>storage systems</subject><subject>successive-cancellation decoding</subject><subject>Systematics</subject><subject>Throughput</subject><issn>0733-8716</issn><issn>1558-0008</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><recordid>eNpdkD1PwzAURS0EEqWwI7FEYmFJec_fYasKhaJKIAGz5ToOBCVxsdOBf0-qIAamu5z79O4h5BxhhgjF9ePLfDGjgHyGHATyAzJBIXQOAPqQTEAxlmuF8picpPQJA8g1nRBc2tRnz6GxMbv1LpQ-ppts3ryHWPcfbWa7Mlu128a3vuttX4fulBxVtkn-7Den5G1597p4yNdP96vFfJ07VkCfy6LaoKosxw2WCj0X1lqhK0Z9JUvAwpesVMopSam0TgNQyx06Klm1kYqyKbka725j-Nr51Ju2Ts43je182CWDclgLUksc0Mt_6GfYxW74zqDgQhdcMDVQMFIuhpSir8w21q2N3wbB7B2avUOzd2hGh0PlYqzU3vs_XGrgBSvYD-mfat0</recordid><startdate>20140501</startdate><enddate>20140501</enddate><creator>Sarkis, Gabi</creator><creator>Giard, Pascal</creator><creator>Vardy, Alexander</creator><creator>Thibeault, Claude</creator><creator>Gross, Warren J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20140501</creationdate><title>Fast Polar Decoders: Algorithm and Implementation</title><author>Sarkis, Gabi ; Giard, Pascal ; Vardy, Alexander ; Thibeault, Claude ; Gross, Warren J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c390t-69fb17fa41b1d71e45aaa58f32ef6d019ed3d77c76226ac8002a4c1c263fb6723</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Algorithms</topic><topic>Architecture</topic><topic>Channels</topic><topic>Complexity theory</topic><topic>Construction</topic><topic>Decoders</topic><topic>Decoding</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Maximum likelihood decoding</topic><topic>Parity check codes</topic><topic>polar codes</topic><topic>Reliability</topic><topic>storage systems</topic><topic>successive-cancellation decoding</topic><topic>Systematics</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sarkis, Gabi</creatorcontrib><creatorcontrib>Giard, Pascal</creatorcontrib><creatorcontrib>Vardy, Alexander</creatorcontrib><creatorcontrib>Thibeault, Claude</creatorcontrib><creatorcontrib>Gross, Warren J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal on selected areas in communications</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Sarkis, Gabi</au><au>Giard, Pascal</au><au>Vardy, Alexander</au><au>Thibeault, Claude</au><au>Gross, Warren J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Fast Polar Decoders: Algorithm and Implementation</atitle><jtitle>IEEE journal on selected areas in communications</jtitle><stitle>J-SAC</stitle><date>2014-05-01</date><risdate>2014</risdate><volume>32</volume><issue>5</issue><spage>946</spage><epage>957</epage><pages>946-957</pages><issn>0733-8716</issn><eissn>1558-0008</eissn><coden>ISACEM</coden><abstract>Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSAC.2014.140514</doi><tpages>12</tpages><oa>free_for_read</oa></addata></record>
fulltext	fulltext
identifier	ISSN: 0733-8716
ispartof	IEEE journal on selected areas in communications, 2014-05, Vol.32 (5), p.946-957
issn	0733-8716 1558-0008
language	eng
recordid	cdi_proquest_journals_1545894537
source	IEEE Electronic Library (IEL) Journals
subjects	Algorithms Architecture Channels Complexity theory Construction Decoders Decoding Field programmable gate arrays Hardware Maximum likelihood decoding Parity check codes polar codes Reliability storage systems successive-cancellation decoding Systematics Throughput
title	Fast Polar Decoders: Algorithm and Implementation
url	http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T05%3A38%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Fast%20Polar%20Decoders:%20Algorithm%20and%20Implementation&rft.jtitle=IEEE%20journal%20on%20selected%20areas%20in%20communications&rft.au=Sarkis,%20Gabi&rft.date=2014-05-01&rft.volume=32&rft.issue=5&rft.spage=946&rft.epage=957&rft.pages=946-957&rft.issn=0733-8716&rft.eissn=1558-0008&rft.coden=ISACEM&rft_id=info:doi/10.1109/JSAC.2014.140514&rft_dat=%3Cproquest_ieee_%3E1620106861%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c390t-69fb17fa41b1d71e45aaa58f32ef6d019ed3d77c76226ac8002a4c1c263fb6723%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1545894537&rft_id=info:pmid/&rft_ieee_id=6804939&rfr_iscdi=true