A 0.039 mm[Formula Omitted] Inverter-Based 1.82 mW 68.6[Formula Omitted]dB-SNDR 10 MHz-BW CT-[Formula Omitted]-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques

• Published in: IEEE journal of solid-state circuits 2014-07, Vol.49 (7), p.1548
• Main Authors: Zeller, Sebastian, Muenker, Christian, Weigel, Robert, Ussmueller, Ussmueller
• Format: Article
• Language: English
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2014.2321063

We present design techniques for the realization of compact, low-power CT-[Formula Omitted]-ADCs in ultra-deep-submicron CMOS: A resonant single-opamp third-order integrator with loss compensation, an inverter-based opamp with digitally assisted biasing and common mode control, a pseudo-differential modulator topology with quasi-1.5-bit quantization, a jitter-noise-reduction DAC with NRZ pulse shape, a mismatch-tolerant IIR quantizer, linearized single-ended FIR-DACs with passive DT compensation, and a rail-to-rail dynamic latched comparator. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented to prove these concepts. The entire active analog circuitry in this minimalistic third-order modulator consists of only ten CMOS inverters. [PUBLICATION ABSTRACT]