Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices

High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as fin...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2014-11, Vol.22 (11), p.2366-2379
Main Authors: Ziabari, Amirkoushyar, Je-Hyoung Park, Ardestani, Ehsan K., Renau, Jose, Sung-Mo Kang, Shakouri, Ali
Format: Article
Language:English
Subjects:
Blurring
Chips
Computation
Finite element method
Finite-element method (FEM)
Geometry
Heat
Heat sinks
heat transfer
Heating
Integrated circuits
integrated circuits (ICs)
Mathematical analysis
Mathematical models
package
power electronics
Silicon
temperature
Temperature distribution
Thermal analysis
thermal management
thermal simulation
Very large scale integration
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Summary:High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2013.2293422