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Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices
High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as fin...
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Published in: | IEEE transactions on very large scale integration (VLSI) systems 2014-11, Vol.22 (11), p.2366-2379 |
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container_title | IEEE transactions on very large scale integration (VLSI) systems |
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creator | Ziabari, Amirkoushyar Je-Hyoung Park Ardestani, Ehsan K. Renau, Jose Sung-Mo Kang Shakouri, Ali |
description | High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time. |
doi_str_mv | 10.1109/TVLSI.2013.2293422 |
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fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_journals_1616985679</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6729105</ieee_id><sourcerecordid>1642208690</sourcerecordid><originalsourceid>FETCH-LOGICAL-c398t-75ceb9cb4f0c59b92072614d1c7732046dc18f3aa5c75c9a416a60ea276392353</originalsourceid><addsrcrecordid>eNpdkU9PwzAMxSsEEjD4AnCJxIVLR_60acNtDAaThpjE4Fp5qTsyuhaSFLRvT8YmDvhiH37vWfaLojNG-4xRdTV7nTyP-5wy0edciYTzveiIpWkWq1D7YaZSxDln9DA6dm5JKUsSRY8iP22_0ZKburPWNItrMgLnybMHbzSBpiQzC40z2Hgye0O7gpoMGqjXzjjyiP6tLUnVWjIF_Q4LLMm48biw4MM4NFZ3xrtfm-2aW_wyGt1JdFBB7fB013vRy-huNnyIJ0_34-FgEmuhch9nqca50vOkojpVc8VpxiVLSqazTHCayFKzvBIAqQ6ogoRJkBSBZ1IoLlLRiy63vh-2_ezQ-WJlnMa6hgbbzhVMhkfRXCoa0It_6LLtbLh0QzGp8lRmKlB8S2nbOmexKj6sWYFdF4wWmyCK3yCKTRDFLoggOt-KDCL-CWTGFaOp-AFLYYQO</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1616985679</pqid></control><display><type>article</type><title>Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Ziabari, Amirkoushyar ; Je-Hyoung Park ; Ardestani, Ehsan K. ; Renau, Jose ; Sung-Mo Kang ; Shakouri, Ali</creator><creatorcontrib>Ziabari, Amirkoushyar ; Je-Hyoung Park ; Ardestani, Ehsan K. ; Renau, Jose ; Sung-Mo Kang ; Shakouri, Ali</creatorcontrib><description>High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2013.2293422</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Blurring ; Chips ; Computation ; Finite element method ; Finite-element method (FEM) ; Geometry ; Heat ; Heat sinks ; heat transfer ; Heating ; Integrated circuits ; integrated circuits (ICs) ; Mathematical analysis ; Mathematical models ; package ; power electronics ; Silicon ; temperature ; Temperature distribution ; Thermal analysis ; thermal management ; thermal simulation ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2014-11, Vol.22 (11), p.2366-2379</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nov 2014</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c398t-75ceb9cb4f0c59b92072614d1c7732046dc18f3aa5c75c9a416a60ea276392353</citedby><cites>FETCH-LOGICAL-c398t-75ceb9cb4f0c59b92072614d1c7732046dc18f3aa5c75c9a416a60ea276392353</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6729105$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Ziabari, Amirkoushyar</creatorcontrib><creatorcontrib>Je-Hyoung Park</creatorcontrib><creatorcontrib>Ardestani, Ehsan K.</creatorcontrib><creatorcontrib>Renau, Jose</creatorcontrib><creatorcontrib>Sung-Mo Kang</creatorcontrib><creatorcontrib>Shakouri, Ali</creatorcontrib><title>Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.</description><subject>Blurring</subject><subject>Chips</subject><subject>Computation</subject><subject>Finite element method</subject><subject>Finite-element method (FEM)</subject><subject>Geometry</subject><subject>Heat</subject><subject>Heat sinks</subject><subject>heat transfer</subject><subject>Heating</subject><subject>Integrated circuits</subject><subject>integrated circuits (ICs)</subject><subject>Mathematical analysis</subject><subject>Mathematical models</subject><subject>package</subject><subject>power electronics</subject><subject>Silicon</subject><subject>temperature</subject><subject>Temperature distribution</subject><subject>Thermal analysis</subject><subject>thermal management</subject><subject>thermal simulation</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><recordid>eNpdkU9PwzAMxSsEEjD4AnCJxIVLR_60acNtDAaThpjE4Fp5qTsyuhaSFLRvT8YmDvhiH37vWfaLojNG-4xRdTV7nTyP-5wy0edciYTzveiIpWkWq1D7YaZSxDln9DA6dm5JKUsSRY8iP22_0ZKburPWNItrMgLnybMHbzSBpiQzC40z2Hgye0O7gpoMGqjXzjjyiP6tLUnVWjIF_Q4LLMm48biw4MM4NFZ3xrtfm-2aW_wyGt1JdFBB7fB013vRy-huNnyIJ0_34-FgEmuhch9nqca50vOkojpVc8VpxiVLSqazTHCayFKzvBIAqQ6ogoRJkBSBZ1IoLlLRiy63vh-2_ezQ-WJlnMa6hgbbzhVMhkfRXCoa0It_6LLtbLh0QzGp8lRmKlB8S2nbOmexKj6sWYFdF4wWmyCK3yCKTRDFLoggOt-KDCL-CWTGFaOp-AFLYYQO</recordid><startdate>20141101</startdate><enddate>20141101</enddate><creator>Ziabari, Amirkoushyar</creator><creator>Je-Hyoung Park</creator><creator>Ardestani, Ehsan K.</creator><creator>Renau, Jose</creator><creator>Sung-Mo Kang</creator><creator>Shakouri, Ali</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7TB</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20141101</creationdate><title>Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices</title><author>Ziabari, Amirkoushyar ; Je-Hyoung Park ; Ardestani, Ehsan K. ; Renau, Jose ; Sung-Mo Kang ; Shakouri, Ali</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c398t-75ceb9cb4f0c59b92072614d1c7732046dc18f3aa5c75c9a416a60ea276392353</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Blurring</topic><topic>Chips</topic><topic>Computation</topic><topic>Finite element method</topic><topic>Finite-element method (FEM)</topic><topic>Geometry</topic><topic>Heat</topic><topic>Heat sinks</topic><topic>heat transfer</topic><topic>Heating</topic><topic>Integrated circuits</topic><topic>integrated circuits (ICs)</topic><topic>Mathematical analysis</topic><topic>Mathematical models</topic><topic>package</topic><topic>power electronics</topic><topic>Silicon</topic><topic>temperature</topic><topic>Temperature distribution</topic><topic>Thermal analysis</topic><topic>thermal management</topic><topic>thermal simulation</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ziabari, Amirkoushyar</creatorcontrib><creatorcontrib>Je-Hyoung Park</creatorcontrib><creatorcontrib>Ardestani, Ehsan K.</creatorcontrib><creatorcontrib>Renau, Jose</creatorcontrib><creatorcontrib>Sung-Mo Kang</creatorcontrib><creatorcontrib>Shakouri, Ali</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ziabari, Amirkoushyar</au><au>Je-Hyoung Park</au><au>Ardestani, Ehsan K.</au><au>Renau, Jose</au><au>Sung-Mo Kang</au><au>Shakouri, Ali</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2014-11-01</date><risdate>2014</risdate><volume>22</volume><issue>11</issue><spage>2366</spage><epage>2379</epage><pages>2366-2379</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2013.2293422</doi><tpages>14</tpages></addata></record> |
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subjects | Blurring Chips Computation Finite element method Finite-element method (FEM) Geometry Heat Heat sinks heat transfer Heating Integrated circuits integrated circuits (ICs) Mathematical analysis Mathematical models package power electronics Silicon temperature Temperature distribution Thermal analysis thermal management thermal simulation Very large scale integration |
title | Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T12%3A27%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Power%20Blurring:%20Fast%20Static%20and%20Transient%20Thermal%20Analysis%20Method%20for%20Packaged%20Integrated%20Circuits%20and%20Power%20Devices&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Ziabari,%20Amirkoushyar&rft.date=2014-11-01&rft.volume=22&rft.issue=11&rft.spage=2366&rft.epage=2379&rft.pages=2366-2379&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2013.2293422&rft_dat=%3Cproquest_ieee_%3E1642208690%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c398t-75ceb9cb4f0c59b92072614d1c7732046dc18f3aa5c75c9a416a60ea276392353%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1616985679&rft_id=info:pmid/&rft_ieee_id=6729105&rfr_iscdi=true |