Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators

Evaluation of the single event upsets (SEUs) impact on SRAM-based FPGAs is a major issue in the adoption of these FPGAs in aerospace applications. In this context, different approaches have been recorded in the literatures, among which the emulation methods are applied most frequently regarding thei...

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Bibliographic Details
Published in:Journal of electronic testing 2014-12, Vol.30 (6), p.739-749
Main Authors: Omidi Gosheblagh, Reza, Mohammadi, Karim
Format: Article
Language:English
Subjects:
Algorithms
CAE) and Design
Circuits and Systems
Computer-Aided Engineering (CAD
Electrical Engineering
Engineering
Field programmable gate arrays
Product testing
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Summary:Evaluation of the single event upsets (SEUs) impact on SRAM-based FPGAs is a major issue in the adoption of these FPGAs in aerospace applications. In this context, different approaches have been recorded in the literatures, among which the emulation methods are applied most frequently regarding their proper cost-effectiveness and time-saving aspects. This paper has proposed a new approach for increasing the SEU emulation rate in the dynamic partial reconfiguration (DPR)-based emulators. Unlike the traditional procedure that emulates the SEU faults only in one loop, the proposed three-level management algorithm (3-LMA) consists of three nested loops. Theoretical analysis and experimental results show that the suggested technique is to some orders of magnitude faster than traditional approach.
ISSN:0923-8174
1573-0727
DOI:10.1007/s10836-014-5489-x