A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

• Published in: IEEE journal of solid-state circuits 2015-08, Vol.50 (8), p.1945-1959
• Main Authors: Song, Keunsoo, Lee, Sangkwon, Kim, Dongkyun, Shim, Youngbo, Park, Sangil, Ko, Bokrim, Hong, Duckhwa, Joo, Yongsuk, Lee, Wooyoung, Cho, Yongdeok, Shin, Wooyeol, Yun, Jaewoong, Lee, Hyengouk, Lee, Jeonghun, Lee, Eunryeong, Jang, Namkyu, Yang, Jaemo, Jung, Hae-kang, Cho, Joohwan, Kim, Hyeongon, Kim, Jinkook
• Format: Article
• Language: English
• Subjects: Bandwidth; Circuits; Clocks; CMOS; Command bus training; DQS oscillator; DRAM; dram interface; Dynamic random access memory; Electric potential; LPDDR4; memory architecture; memory SERDES; Mobile communication; Mobile communication systems; Oscillators; Power consumption; Random access memory; read DQ calibration; tDQS2DQ; Timing; Training; Voltage; write leveling; write training; ZQ calibration
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2429588

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.