Analytical Calculation of Jitter Probability Density at Multistage Output Buffers Due to Supply Voltage Fluctuations

The jitter probability density function (PDF) at multistage output buffers due to supply voltage fluctuations is analytically derived. For experimental validation, an integrated circuit (IC) is designed, fabricated, and assembled in a printed circuit board (PCB). The on-chip supply voltage fluctuati...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on electromagnetic compatibility 2015-08, Vol.57 (4), p.796-806
Main Authors: Park, Eunkyeong, Kim, Hyungsoo, Shim, Jongjoo, Kim, Yong-Ju, Kim, Yun-Saing, Kim, Jingook
Format: Article
Language:English
Subjects:
Clock tree
Integrated circuit modeling
Jitter
MOSFET
multistage
power distribution network (PDN)
power-supply-induced jitter (PSIJ)
Probability density function
probability density function (PDF)
repeater
signal integrity
Voltage measurement
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The jitter probability density function (PDF) at multistage output buffers due to supply voltage fluctuations is analytically derived. For experimental validation, an integrated circuit (IC) is designed, fabricated, and assembled in a printed circuit board (PCB). The on-chip supply voltage fluctuations are extracted from the simultaneous measurements at the pads on IC and PCB and used to calculate the jitter PDF of the multistage buffers. Also, characteristics of the output channels are measured and modeled with the separately designed channel pattern. Finally, the jitter PDFs for multistage buffers are calculated and compared with the measured jitter histograms.
ISSN:0018-9375
1558-187X
DOI:10.1109/TEMC.2015.2403294