An Analysis of Hypermesh NoCs in FPGAs

• Published in: IEEE transactions on parallel and distributed systems 2015-10, Vol.26 (10), p.2643-2656
• Main Authors: Binesh Marvasti, Mohammadreza, Szymanski, Ted H.
• Format: Article
• Language: English
• Subjects: Algorithms; analytic model; Analytical models; area; delay; Delays; energy; Field programmable gate arrays; FPGA; graph model; Hypercubes; Hypermesh; Network-on-Chip; Optical switches; parallel algorithm; Pipelines; power; Wires
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2014.2360194

Accurate analytic models for the area, delay and power of the Hypermesh NoC topology, realized with the Altera family of FPGAs, are presented. Hypermeshes are based on the concept of hypergraphs, which consist of a set of nodes and a set of hyperedges, where the hyperedges represent low-latency switches which interconnect multiple nodes with deterministic latencies. Three different switch designs for the hyperedges are proposed and evaluated. Two parallel algorithms are considered; (a) the Bitonic sorting algorithm, and (b) the FFT parallel algorithm. The analytic models are shown to be very accurate, typically within 6 percent. The 2D Hypermesh is compared to the 2D layouts of the binary hypercubes (BHC) and generalized hypercubes (GHC) in terms of area, energy per algorithm, and the Energy-Area product . The Energy-Area product is proposed as an useful design metric to evaluate NoCs, which combines both the cost and the performance metrics of an NoC into one. Our analysis indicates that the 2D Hypermeshes generally have considerably lower area, energy, and Energy-Area product compared to the 2D layouts of the Hypercubes.