Common-Mode Voltage Reduction of Three-Level Four-Leg PWM Converter

• Published in: IEEE transactions on industry applications 2015-09, Vol.51 (5), p.4006-4016
• Main Authors: Chee, Seung-Jun, Ko, Sanggi, Kim, Hyeon-Sik, Sul, Seung-Ki
• Format: Article
• Language: English
• Subjects: common-mode current (CMC); common-mode voltage (CMV); Computers; Electronics; Harmonic analysis; pulse width modulation (PWM); push-pull PWM (PPPWM); sinusoidal PWM (SPWM); Software; Space vector pulse width modulation; space vector PWM (SVPWM); Switches; three level four leg converter; Topology
• ISSN: 0093-9994; 1939-9367
• DOI: 10.1109/TIA.2015.2422771

This paper presents a carrier-based pulsewidth modulation (PWM) method that reduces the common-mode voltage (CMV) of a three-level four-leg converter. Based on an analysis of space vector PWM (SVPWM) and sinusoidal-PWM switching patterns, the fourth-leg pole voltage of a three-phase converter, known as the "f pole voltage," is manipulated to reduce the CMV. To synthesize the f pole voltage for the suppression of the CMV, positive and negative pole voltage references of the f leg are calculated. In addition, the offset voltage to prevent distortion of the a, b, and c phase voltages regarding the neutral point is deduced. The proposed PWM strategy can be easily implemented in the software of a DSP-based converter control. The three-level four-leg converter with the proposed PWM algorithm results in a remarkable reduction in the peak-to-peak value of the CMV. From the simulation and the experimental results, the peak-to-peak value of the CMV when using the proposed PWM method is 33% compared to that when using the SVPWM method, while the number of CMV transitions during the switching period in the proposed PWM method is only 25% of that when using the SVPWM method.