Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

• Published in: IEEE transactions on electron devices 2015-10, Vol.62 (10), p.3229-3236
• Main Authors: Yijiao Wang, Al-Ameri, Talib, Xingsheng Wang, Georgiev, Vihar P., Towie, Ewan, Amoroso, Salvatore Maria, Brown, Andrew R., Cheng, Binjie, Reid, David, Riddet, Craig, Shifren, Lucian, Sinha, Saurabh, Yeric, Greg, Aitken, Robert, Xiaoyan Liu, Jinfeng Kang, Asenov, Asen
• Format: Article
• Language: English
• Subjects: CMOS; CMOS integrated circuits; electrostatics; Logic gates; Mathematical model; Mobile communication; nanowire transistors (NWs); Quantum capacitance; quantum effects; TCAD; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2015.2470235

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.