Impact of Crystallization Method on Poly-Si Tunnel FETs

• Published in: IEEE electron device letters 2015-10, Vol.36 (10), p.1060-1062
• Main Authors: Yi-Hsuan Chen, Ma, William Cheng-Yu, Jer-Yi Lin, Chun-Yen Lin, Po-Yang Hsu, Chi-Yuan Huang, Tien-Sheng Chao
• Format: Article
• Language: English
• Subjects: Crystallization; Electric potential; Electron traps; Junctions; Logic gates; metal-induced lateral crystallization (MILC); poly-Si thin-film transistor (poly-Si TFTs); Semiconductors; Silicon; Thin film transistors; trap density; tunnel field-effect-transistor (TFET)
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2015.2468060

In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (Nit) and bulk traps (N GB ). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit ~4.5× higher ON-state current ION, subthreshold swing reduction ΔS.S. ~202 mV/decade, and larger ~7.2× ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced N it ~ 0.60× and a reduced N GB ~ 0.36×, respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics.