A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

• Published in: IEEE journal of solid-state circuits 2015-10, Vol.50 (10), p.2451-2462
• Main Authors: Choi, Woong, Kang, Gyuseong, Park, Jongsun
• Format: Article
• Language: English
• Subjects: Application-specific memory; Computer architecture; Couplings; Decoding; eDRAM; embedded memory; gain cell; Hardware; IEEE 802.11n Standard; reference voltage generator; Semiconductors; Transistors; Viterbi algorithm; Viterbi decoder
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2454241

This paper presents a Viterbi-specific 2T gain cell- based embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.