Hardware Optimization of Compressed Sensing Based on FPGA

Realized the compressed sensing based on FPGA. The system sparseed the image date by using the 3-level lifting wavelet transform, measured the sparse data, by using the hadamard matrix, and reconfigured the data by using the orthogonal matching pursuit. The system realized the compressed sensing bas...

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Bibliographic Details
Published in:Sensors & transducers 2013-12, Vol.25, p.73
Main Authors: Li-Na, Shang, Sheng-Ying, Zhao, Cui, Zhang, Guang-Chun, Gao, Kai, Xiong
Format: Article
Language:English
Subjects:
Algorithms
Data processing
Dictionaries
Field programmable gate arrays
Fourier transforms
Information theory
Multiplication & division
Signal processing
Theory
Online Access:Get full text
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Summary:Realized the compressed sensing based on FPGA. The system sparseed the image date by using the 3-level lifting wavelet transform, measured the sparse data, by using the hadamard matrix, and reconfigured the data by using the orthogonal matching pursuit. The system realized the compressed sensing based on NIOSII, optimized the hardware structure of stochastic measure matrix. It reduced the usage of resource and kept the speed. The system has the better reconfiguration effect, less distortion and uses less hardware resource.
ISSN:2306-8515
1726-5479